1. Field of the Invention
The present invention relates to a flash memory structure, and more particularly, to a novel flash memory structure having fewer global bit lines and smaller layout size.
2. Description of the Prior Art
Please refer to FIG. 1, which is a diagram of a block of a conventional flash memory device 100. The flash memory device 100 comprises a plurality of local bit lines 121-126, a plurality of word lines 131-133, a plurality of global bit lines 141-146, and a plurality of memory units 101-115 arranged in an array. As is well known in the art, each memory unit 101-115 comprises a memory cell 151, a select switch 152, and a memory cell 153.
In addition, each local bit line 121-126 is respectively coupled to each global bit line 141-146 through a plurality of switches 161-166. Each memory unit 101-115 is operated according to the supplying voltage of the word lines 131-133 and the global bit lines 141-146. Furthermore, the switches 161-166 are implemented by MOSFETs. And the gates of switches 161, 163, and 165 are coupled to the conducting line 172, and the gates of switches 162, 164, and 166 are coupled to the conducting line 173.
When memory cell 151 of memory unit 101 is accessed, the switches 161 and 162 are both turned on by conducting lines 172 and 173, and a voltage 0V is applied to the global bit line 141, and another voltage 1.2V is applied to the global bit line 142. Therefore, the local bit line 121 is coupled to 0V through the switch 161, and the local bit line 122 is coupled to 1.2V through the switch 162. In addition, the word line 131 is supplied by a high voltage such that the memory unit 101 can be selected. Therefore, the signal path (shown as the arrow in FIG. 1) can be established.
The aforementioned flash memory structure 100 has a serious problem, however. Please refer to FIG. 1 again. One global bit line occupies the space of one memory unit column. Because semiconductor manufacturing techniques are constantly improving, the memory unit 101-115 can be formed much smaller than before. But the width of the global bit line 141-146 cannot be narrowed easily. Therefore, the size of the memory array is limited by the pitch of the global bit lines 141-146.
In order to solve the above-mentioned problem, another memory structure is disclosed. Please refer to FIG. 2, the flash memory device 200 comprises a plurality of local bit lines 221-226, a plurality of word lines 231-233, a plurality of global bit lines 241-243, and a plurality of memory units 201-215 arranged in an array. As mentioned previously, each memory unit 201-215 comprises a memory cell 251, a select switch 252, and a memory cell 253.
In FIG. 2, the local bit lines 221 and 223 are coupled to the global bit line 241 through switches 261 and 263. Similarly, the local bit lines 222 and 224 are respectively coupled to the global bit line 242 through switches 262 and 264.
To access the memory cell 251 of the memory unit 201, the global bit line 241 is applied by 0V and global bit line 242 is applied by 1.2V. Therefore, the local bit line 221 is coupled to 0V through switch 261 and the local bit line 262 is coupled to 1.2V through switch 262. The word line 231 is supplied by a high voltage such that the memory unit 251 can be selected. The signal path shown in the arrow in FIG. 2 can be established.
Although the problem of global bit lines pitch is solved, another problem occurs. Any operation on the memory unit 201 needs two global bit lines 241 and 242. It is impossible to access memory unit 201 and 203 at the same time as in FIG. 1. The efficiency of the flash memory device 200 is reduced.